Hands-on Visualizers

Interactive Physics & Timing Simulators

Experiment in real-time with device equations, voltage transfer curves, and clock timing constraints.

1. MOSFET I-V Characteristics Simulator

Observe pinch-off, linear vs saturation modes, and channel length modulation.

Region: Saturation

I_D: 0.000 mA

V_OV: 0.00 V

g_m: 0.00 mS

Gate-Source Voltage (V_GS): 2.0 V

Drain-Source Voltage (V_DS): 1.8 V

Threshold Voltage (V_th): 0.6 V

Aspect Ratio (W / L): 10

Process Transconductance (µ_n C_ox): 200 µA/V²

Channel Length Modulation (λ): 0.05 V⁻¹

Evaluate switching threshold V_M and high/low noise margins (NM_L, NM_H).

V_M: 0.900 V

NM_L: 0.720 V

NM_H: 0.720 V

Symmetric

Supply Voltage (V_DD): 1.8 V

NMOS Threshold (V_tn): 0.4 V

PMOS Threshold (|V_tp|): 0.4 V

Transconductance Ratio (k_p / k_n): 1.0

Visualize clock skew, data arrival, setup windows, and hold races on live waveforms.

Setup Slack: +2.80 ns

Hold Slack: +6.40 ns

Data Arrival: 7.70 ns

All Timing Constraints Met! Timing closure achieved for this path.

Clock Period (T_clk): 10.0 ns

Clock Skew (T_skew): 0.5 ns

Launch FF Delay (T_cq): 1.2 ns

Combinational Logic Delay (T_comb): 6.5 ns

Setup Time (T_setup): 1.0 ns

Hold Time (T_hold): 0.8 ns